Device for validating an integrated circuit

ABSTRACT

A device ( 10 ) for validating a circuit ( 1 ) comprising at least one microprocessor ( 3 ) and a specialized unit ( 2 ) provided with registers includes a base ( 11 ) for receiving the circuit, a memory ( 4, 5 ) simulating an external memory with which the circuit is intended to cooperate and a computer ( 20 ) controlling the validation. The memory ( 4, 5 ) contains software for processing data received by the circuit and instructions for executing a validation sequence, making it possible to form a data flow representing a flow received by the circuit in normal operation, to compare data contained in registers of the circuit with theoretical values and to supply a signature representing a result of these comparisons.

FIELD OF THE INVENTION

[0001] The invention concerns the field of devices and methods intendedto determine whether a circuit comprising in particular a microprocessorand possibly one or more specialized units fulfilling logical dataprocessing functions is or is not able to function correctly. It alsoconcerns an apparatus, for example a digital television decoder,incorporating such a circuit and an associated memory.

[0002] Patent application WO 99/48001 presents an improvement to amicroprocessor validation method known as the series check technique. Ina paragraph of the cited application, devoted to the description of theprior art, checking the correct functioning is carried out by means ofspecific software which is known as an error detection monitor, isexecuted by a microprocessor to be validated, and is loaded into themicroprocessor to be validated in order to interface an error detectionsystem included in an error detection computer. The error detectionmonitor executed by the microprocessor to be validated is softwareassisting the error detection system providing the access functions tothe memories and registers of the microprocessor to be validated.Resources of the microprocessor to be validated are used by the errordetection monitor and by the error detection computer, such as memoryresources containing software and data necessary for the error detectionmonitor and the error detection system.

[0003] The disadvantage of such a system, indicated in the applicationWO 99/48001, is that it uses resources and memory within the device tobe validated and that consequently the cost of using such a device isincreased.

[0004] The invention relates to a device affording a fast validation oflogic circuits, with a throughput of the order of several thousands ofcircuits per hour, making it possible to validate an entire productioncircuit by circuit, the probability of correct functioning in the eventof positive validation being almost equal to 1.

[0005] The invention relates to a device for validating a data flowprocessing circuit, said circuit having inputs/outputs and includingfirstly at least one microprocessor intended to cooperate with a memoryexternal to the circuit and secondly at least one specialized unit forperforming a partial processing of the data, the microprocessor or theunit comprising registers (R_(i)-R_(n)), which device is characterizedin that it includes a read memory containing, in addition to anoperating system necessary for the functioning of the microprocessor andthe specialized unit:

[0006] a set of data suitable to supply a known data flow representing adata flow which could be received by the circuit in normal operation,

[0007] a set of theoretical values which is to appear during processingat at least one given instant in at least one of the registers of themicroprocessor or the specialized unit,

[0008] instructions for effecting a validation, including instructionsfor loading the data to be processed by organizing the data in a flowand sequentially comparing values present in registers with saidtheoretical values, and

[0009] instructions for supplying a signature representing results ofsaid comparisons.

[0010] Preferably, in order to reduce the number of instructions of thedata processing software devoted to the validation included in saidsoftware, a validation computer is coupled to a base intended to receivethe circuit to be validated. This computer supplies the clock of thecircuit to be validated, initiates and terminates a logical validationsequence, and receives, by means of the outputs of the circuit to bevalidated, a value representing a signature representing a result ofcomparisons made by the microprocessor included in the circuit to bevalidated.

[0011] The comparison is made between real register values of themicroprocessor or the specialized unit, said values appearing atpredetermined instants during the processing in one of the registers,and theoretical values stored in the read memory in order to deducetherefrom a state of functioning or non-functioning of the circuit to bevalidated.

[0012] Thus, in a validation device according to the invention, thecircuit to be validated is provided with operating software whichcomprises, in addition to instructions strictly necessary for thefunctioning of the circuit, instructions intended to perform anautovalidation of the circuit. However, this inclusion of additionalinstructions comprises only instructions intended to load known data byorganizing them in a known flow, comparing the content of certainregisters with stored values and supplying a result of the comparisonsin the form of a signature. The normal functioning of the circuit to bevalidated for the processing of the data is practically unchangedthereby. These additional instructions require only minimal memory spaceand do not interfere with the dynamic functioning of the circuit.Preferably, the data necessary for the constitution of the data flow andthose necessary for the comparisons appear only in the validation deviceand not in the memory associated with the circuit to be validated.

[0013] The invention also concerns an apparatus, in particular adecoder, incorporating a circuit comprising at least one microprocessorand memory means associated with the circuit, the memory meanscontaining instructions for loading, during a test phase, datarepresenting data normally received by the apparatus in operation andfor comparing data contained in the memory means with data contained inat least one register included in the circuit. According to theinvention, it is the circuit which, during the validation examinationsuccessfully completed by a validation device, performs operations inaccordance with its operating conditions and its connections in theapparatus in which the circuit is to be mounted.

[0014] The invention also relates to a method of validating a circuitincorporating at least one specialized unit and at least onemicroprocessor provided with registers, according to which method themicroprocessor executes, in addition to the data processinginstructions, instructions whose purpose is to provide information onthe functioning of the circuit, consisting of instructions for importingdata by organizing them in an incoming flow, representing a data flowwhich could be received by the circuit in normal operation, comparingtheoretical values with actual values contained in registers of thecircuit to be validated, and supplying a signature indicating results ofthese comparisons.

[0015] Advantageously, such a method will comprise a prior phase duringwhich connections of the circuit to be validated are tested.

[0016] An embodiment of the invention will be now described by way ofexample with reference to the attached drawings to which, however, theinvention is not restricted.

[0017]FIG. 1 depicts schematically an example of a circuit to bevalidated;

[0018]FIG. 2 depicts schematically an example of a circuit validationdevice according to the invention;

[0019]FIG. 3 depicts schematically a specific embodiment of the circuitvalidation device according to the invention;

[0020]FIG. 4 depicts schematically the specific embodiment of thevalidation device depicted in FIG. 3 in a first configuration intendedto test the circuit structurally;

[0021]FIG. 5 depicts schematically the specific embodiment of thevalidation device depicted in FIG. 3 in a second configuration intendedto test the circuit functionally.

[0022]FIG. 1 depicts an example of a circuit 1 to be validated. Thecircuit 1 comprises one or more input/output interfaces 6 forcommunicating with memories or other circuits, and a specialized circuittree 2 dedicated to performing functions, for example, logic functions.The circuit to be validated belongs, for example, to a digitaltelevision decoder receiving in digital form a flow of data, possiblycompressed or scrambled, representing video signals, and processingthese data in order to recreate a clear non-compressed video signal inwhich is delivered in digital or analog form. In this case, thespecialized circuits 2 could be, by way of a non-limitating example, anMPEG flow processing circuit incorporating a circuit for unscramblingscrambled digital video transmissions, filters for example of sectionsor on headers of elementary flows packaged in elementary flowtransportation packets.

[0023] The circuits 2 of the tree function under the control of amicroprocessor 3 comprising registers R1, R2, R3 . . . Rn.

[0024]FIG. 2 depicts a device 10 for validating a circuit 1.

[0025] According to the invention a validation tool 10 is created,reproducing the actual operating environment of the circuit 1 to betested. In the case envisaged here by way of example, where the circuitforms part of a decoder, it has not been necessary to reproduce forexample a tuner providing the detection of the signals to be received.This part is replaced by a memory 5, for example of the ROM type,containing data representing data detected by the tuner. The quantity ofdata stored makes it possible to simulate a reception period and adiversity of presentations of the information detected which aresufficient for the execution of the validation. The memory containsoperating software of the microprocessor 3 or of specialized circuits 2for performing dedicated functions on the data or on data alreadypartially processed. The memory 5 also contains values corresponding totheoretical values which must appear in registers of the microprocessor3 or in specialized circuits 2 when the circuit 1 is operating correctlyor is receiving the particular data flow coming from the memory.

[0026] A computer 20 is also added, so as to manage the validation checkon the circuit 1 to be validated. This computer 20 initiates the checkand ends it by giving information on the result of the validation, thisresult being delivered by the microprocessor 3 of the circuit 1 to bevalidated. The result is then used by displaying, for example on adisplay (not shown), a result of the check.

[0027] The validation device 10 according to the invention comprises abase 11 for receiving a circuit 1 to be validated. The memories 4 and 5form part of the device 10 and are connected in the same way as to theactual mounting circuit of the circuit 1 to be validated. These memories4, 5 are connected to the circuit 1 by a data link 7 and an address link8. The ROM memory 5, possibly in several parts 51-54 as shown in FIGS.3-5, contains operating software of the microprocessor 3 (operatingsystem). As indicated above it also contains values representing valueswhich, in normal operation, could be received by the circuit 1. In thepresent example, concerning a digital television decoder, the data arearranged so as to be able to be put in the form of an MPEG flow. Thememory 5 also contains values corresponding to theoretical values whichmust appear in registers of the microprocessor or specialized circuitswhen the circuit is functioning correctly or is receiving the particulardata flow coming from the memory.

[0028] Preferably the device 10 also comprises a manipulator 30. This isa mechanical means of manipulating logic circuits 1 to be validated. Themanipulator 30 grips the circuits 1, for example by means of a sucker,installs them on the base 11, grips them once again at the end ofvalidation and places them in a path reserved for the circuits 1 whichare declared in order or in a reject basket. The manipulator 30 iscontrolled by the validation computer 20.

[0029] In the preferred embodiment of the invention, the validation ispreferably carried out in two stages. To this end, as depicted in FIG.3, a two-position switch 22 is interposed between the validationcomputer 20 and the base 11.

[0030] In the two positions the links 12, 13, 14 between the computer 20and the circuit 1, relating to functions of positioning theinputs/outputs of the circuit 1, of initialization, and of usingrespectively, do not pass through the switch 22.

[0031] In a first position of the switch 22 depicted in FIG. 4, thecomputer 20 and the circuit 1 are coupled by links 15, 16, 17 for linecontrol, addresses and data, respectively, said links being establishedthrough the switch 22.

[0032] In a second position of the switch 22, depicted in FIG. 5, thenormal functioning of the circuit 1 is monitored. A data link 7 passingthrough the switch 22 couples the circuit 1 to the data of the memory 5,via a converter 19 or to the memory 4. The function of the converter 19is to adapt the logic level of the data coming from the memory 5 to alevel suitable for the circuit 1. An address line 8, and a control line9 passing through the switch 22, couple the circuit 1 to the memory 4and via a buffer 18, to the memory 5.

[0033] The memories 51-54 together forming the memory 5, the memory 4,the buffer 18, and the converter 19 form together an embodiment of thememory means 50. Thus, the circuit 1 is coupled by means of the base 11to the memory means 50. It should be noted that the memory means 50 arecomparable to memory means working with the circuit 1 to be validated.The content of the memory means 50 is however more important in thatthey comprise the data for forming the flow and the register contentcomparison values.

[0034] In the first position, a structural validation is carried out inorder to validate essentially the connections and the dynamic behaviorof a few functions using one or more specialized circuits 2 of thecircuit 1. The dynamic behavior of the functions is carried out usingconfigurations coming from the validation computer 20.

[0035] In the second position the validation is carried out from datacontained in the memories 4 and 5 while using the operating software ofthe circuit 1. In this second configuration, autoexecutable software ofthe microprocessor 3 of the circuit 1 connects the circuit 1 to anoperating system loaded in the memory 4. After this initialization theinstructions for normal data processing are executed on the datacontained in the memory 5 and introduced into the circuit to bevalidated 1. The operating software of the circuit 1 comprises for thispurpose special instructions intended for the execution of thevalidation. These instructions organize data contained in the memory 5and a flow representing the MPEG flow under varied conditions, forexample, and non-limitating, scrambled or in clear, static or rapidlymoving images. The operating circuit of the circuit 1 also comprisesinstructions for making comparisons between theoretical values containedin the memory and actual values contained in designated registers.

[0036] The check on the dynamic functioning of the whole of the circuit1 according to this second configuration of the device 10 takes place asfollows:

[0037] the computer 20 managing the check initializes the circuit 1 tobe validated and controls the switch 22 in order to place it in thesecond position.

[0038] The microprocessor 3 of the circuit to be validated starts theloading of instructions, and loads the operating software present in theROM memory 5. The microprocessor 3 of the circuit to be validated thenimports the data contained in the ROM memory by organizing them in adata flow transmitted at the normal speed at which these data travel. Ithas already been seen that the operating software of the microprocessorto be validated comprises, in addition to the normal instructions forprocessing these data, instructions for:

[0039] comparing the theoretical values stored in the ROM memory 5 withthe actual values contained in the registers of the microprocessor 3 orspecialized circuits 2 at predetermined processing instants,

[0040] sending to the management computer 10 a signature indicating thestate of the comparisons between theoretical values and actual values.

[0041] If all the actual values are equal to the theoretical values,which results in a signature having a known value of the managementcomputer 10, then the microprocessor is declared to be in order by theinspection management computer, and if this is not the case themicroprocessor is declared faulty.

[0042] The validation computer 20 pronounces the end of the validationand its result. The computer 20 then actuates the manipulator 30, whichremoves the circuit which has just been tested, and directs it towardsthe good or faulty circuits according to the result of the validationand puts in place a new circuit 1 to be validated. By way of indicationthe device 10 according to the invention makes it possible to validateseveral thousands of circuits per hour.

1. A device for validating a data flow processing circuit (1), saidcircuit having inputs/outputs (6) and including firstly at least onemicroprocessor (3) intended to cooperate with a memory external to thecircuit and secondly at least one specialized unit (2) for performing apartial processing of the data, the microprocessor (3) or the unit (2)comprising registers (R_(i)-R_(n)), which device is characterized inthat it includes a read memory (4, 5) containing, in addition to anoperating system necessary for the functioning of the microprocessor andthe specialized unit: a set of data suitable to supply a known data flowrepresenting a data flow which could be received by the circuit innormal operation, a set of theoretical values which is to appear duringprocessing at at least one given instant in at least one of theregisters of the microprocessor or the specialized unit, instructionsfor effecting a validation, including instructions for loading the datato be processed by organizing the data in a flow and sequentiallycomparing values present in registers with said theoretical values, andinstructions for supplying a signature representing results of saidcomparisons.
 2. A validation device as claimed in claim 1, including avalidation computer (20) coupled to a base (11) intended to receive thecircuit (1) to be validated.
 3. A validation device as claimed in claim2, also including switching means (22) controlled by the validationcomputer (20), said means (22) allowing a selection between a firstconfiguration in which the circuit (1) to be validated hasinputs/outputs connected to the validation computer, and a secondconfiguration in which the same inputs/outputs are connected to theexternal memory.
 4. A validation device as claimed in claim 2, alsoincluding a manipulator (30) for placing and removing circuits (1) to bevalidated, said manipulator being controlled by the validation computer(20).
 5. A method of validating a circuit (1) incorporating at least onespecialized unit (2) and at least one microprocessor (3) provided withregisters, according to which method the microprocessor executes, inaddition to the data processing instructions, instructions whose purposeis to provide information on the functioning of the circuit, consistingof instructions for importing data by organizing them in an incomingflow, representing a data flow which could be received by the circuit innormal operation, comparing theoretical values with actual valuescontained in registers of the circuit to be validated, and supplying asignature indicating results of these comparisons.
 6. A method asclaimed in claim 5, characterized in that it comprises a prior phaseduring which connections of the circuit to be validated are tested. 7.An apparatus incorporating a circuit comprising at least onemicroprocessor and memory means associated with the circuit, the memorymeans containing instructions for loading data representing datanormally received by the apparatus in operation and for comparing datacontained in the memory means with data contained in at least oneregister included in the circuit.